The present invention relates to a bus system for information processing systems such as personal computers, work stations, word processors, process controllers and the like. The invention is further concerned with a method of controlling the bus system.
There is described a variety of data transactions carried out by resorting to a combination of a single address mode, a block transfer mode and a general transfer mode in a publication entitled "IEEE Standard Backplane Bus Specification for Multiprocessor Architectures: Future bus", ANSI/IEEE Std 896.1-1987, pp. 73-119.
In conjunction with known bus systems for information processing systems as well as bus control systems such as a bus arbitration control system for deciding which of bus-connected modules should become a next bus master, i.e. should gain the control of a system bus, there are adopted a mode referred to as a single address mode in which only the data that corresponds to a single address is transferred with a single beat (i.e. per tenure), and a mode referred to as a burst transfer mode or a block transfer mode in which data is transferred consecutively to one or a plurality of addresses during a single transaction tenure, wherein the species of the modes which are to be made use of in the bus for the data transfer can be discriminatively identified with the aid of a mode line. In this connection, reference may be made to "IEEE Standard for a simple 32-Bit Backplane BUS: NuBus", ANSI/IEEE Std 1196-1987 (1988), pp. 21-62. According to the prior art technique, the right of using the bus (referred to as the bus mastership or bus ownership) once acquired through arbitration allows only one block transfer, word transfer, broadcast transfer or the like per transaction. Accordingly, when the data transfer is to be performed a number of times by changing or modifying the address arbitrarily, the bus mastership acquisition process (i.e. the process for acquiring the right of using the bus) through arbitration control must be performed a corresponding number of times.
According to the standards specified in the second mentioned publication, it is noted that the data width or length corresponding to a unit address is set to be smaller than that of the data bus. More specifically, while the data bus width is 32 bits, the unit address given by the least significant bits thereof corresponds to a data width of 8 bits, i.e. 1 byte, wherein the address space is 2.sup.32 bytes and hence 2.sup.30 words, assuming that one word is 32 bits (because 2.sup.32 /(32/8)=2.sup.30). Further, when data of a width smaller than that of the data bus is to be transferred, it is required to control the data transfer by making use of the least significant bits of the address and a bus control line in addition to an address data line. In other words, in order to carry out the data transfer on an 8-bit basis or on a 16-bit basis, the control therefor requires the two least significant bits and two bus control lines.
Devices connected to the bus system having the two modes such as mentioned above must naturally be compatible with both modes, which however gives rise to problems that the control procedure as involved becomes complicated and the amount of hardware for the control circuit is correspondingly increased.
Besides, in the prior art techniques mentioned above, no consideration is paid to applications such as distribution of a large amount of data to a plurality of addresses, and there arises a problem that the bus mastership (i.e. the right of using the bus) has to be newly acquired through arbitration control every time the address is modified or changed.
Additionally, in the case of the prior art bus systems, the size of the memory space capable of being addressed is limited to 2.sup.32 bytes by the bit width of the unit data to be transferred. On the other hand, when the data of a width smaller than that of the data bus is to be transferred, both the address line multiplexed with the data line and the bus control line have to be controlled. As a consequence, for a bus-connected device capable of transferring the data having the same width as that of the data bus, the least significant bits of the address become redundant, with the result that the memory space capable or being addressed is limited to an unnecessarily reduced size, while for a bus-connected device destined for handling data of a smaller width than the data bus, control must be performed for both the address/data multiplex line and the bus control lines, presenting a problem that the control circuit configuration is inevitably very complicated.